T he interconnect delay
(propagation time along a trace) is sometimes more important
than the signal propagation time through individual
components. Standard reference sources (Motorola's MECL
System Design Handbook, for example1) give several formulas
that relate to the propagation delay of a signal along a
trace on a circuit board. These formulas have been combined
and summarized in Figure 1. The first part of the formula
provides the basic propagation time under unloaded
conditions. In that formula, a = 1, b = 0 for stripline
configurations and a = 0.475, b = 0.67 for microstrip.
Figure 1-Formula for
propagation delay along a trace.
The second part of the formula incorporates the slowing of
signals due to the capacitive loading along the line. This
capacitive loading is caused by circuit loads on the line and
stray, parasitic capacitances.
People tend to use 2 nsec./ft. as a standard rule of thumb
for propagation delay when designing circuits. However, this
figure might be off by as much as 50%, depending on design
specifics.
The first important variable in this equation is er, the
relative dielectric coefficient. A value of 4.2 for standard
FR-4 board material is often used. Actual values can easily
range from 4.0 to 4.4 (or more) in the real world, and er
even varies within a layer as a result of temperature and
pressure effects during fabrication. This range results in an
uncertainty of tpd of approximately 5%, or about 0.1
nsec./ft. That's 8.3 psec./in., or 100 psec. in a 12-inch
line.
The second important factor is Cd, the sum of the
capacitance effects of the loads on the line. A fanout of
eight loads of about 5 picoferads each on a 12-inch line can
slow tpd by as much as 50% (1 nsec./ft. or 83 psec./in). The
calculation of the exact amount requires a calculation of Co,
which depends on er and the board interlayer geometries.
The bottom line is that before the delay along a line can
be adjusted accurately to meet circuit needs, the actual tpd
along the line must be known. The actual tpd depends, among
other things, on the design that is created (the path
lengths) and the fabrication processes that are used.
My company can trim a line length as close as 1 mil, which
is within a fraction of a picosecond. Since, in practice, the
uncertainty of tpd is as much as 80 psec. in an inch, design
tolerances can be almost two orders of magnitude tighter than
other sources of uncertainty!
So, what does the circuit design engineer do? First,
understand the limitations of accurately estimating tpd
before adjusting signal delay times by adjusting line
lengths. Then, work closely with your board house. I have
found that only a small fraction of board shops really
understand these concepts and their processes well enough to
help their customers meet very tight requirements.
Limits on Adjustments
There is a lower limit on propagation time. It's hard to
make a trace shorter than the straight line connecting two
points! But, you can add time to a trace by increasing its
length. Up to available surface area, no limit exists on how
much time may be added.
My company can adjust an individual line (or match a
differential pair of lines) as close as 1 mil (0.001) without
much difficulty, which is about 0.2 psec. Although we can
adjust lengths even tighter than this, the benefits are
seldom worth the effort.
Figure 2-- Alternative
ways to route traces to add propagation time to a line.
How To Route Trace Lengths
Figure 2 illustrates three alternative ways a trace may be
routed to add propagation time to a signal line. In
February's column, "Right-Angle Corners," I pointed
out why alternative (b) is undesirable-it looks just like an
antenna. Alternative (a) is even worse! It looks like a dish
antenna. The preferred way to add propagation time to a trace
is illustrated in (c), a randomly routed line. It may be a
good idea to "guard band" such a trace to control
crosstalk with other traces and to minimize susceptibility to
radiated energy into the trace. 1MECL System Design Handbook,
Motorola, 1988, p. 45, 48 and 129.
